Enhancement of iso-via reliability

ABSTRACT

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material that surrounds at least part of the via so as to render the via compressive where the via contacts the wiring line. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

BACKGROUND

The exemplary embodiments relate to enhancement of a via's reliabilityand, more particularly, relate to a structure and method of enhancingthe reliability of vias by making the bottom of the vias be undercompressive stress.

In a semiconductor structure, vias may be the weakest link forinterconnect reliability. In the latest semiconductor technology, viasare smaller and so are more susceptible to voids and opens. Under theground rules for the latest semiconductor technology, there may not beroom for redundant vias so there may be only one via, an “iso-via”, thatprovides the connection between wiring levels. Due to the lack ofredundancy, any iso-via failure can cause a circuit, or even the entiresemiconductor chip, to fail.

BRIEF SUMMARY

The various advantages and purposes of the exemplary embodiments asdescribed above and hereafter are achieved by providing, according to afirst aspect of the exemplary embodiments, a semiconductor structurewhich includes a semiconductor base including a plurality ofsemiconductor devices and a back end of the line wiring layer. The backend of the line wiring layer includes a wiring line; an interlayerdielectric (ILD) layer on the wiring line; a via extending through theILD to communicate with the wiring line; a metal filling the via and incontact with the wiring line; and a compressive reliability enhancementmaterial surrounding at least part of the metal-filled via to make abottom of the metal-filled via that contacts the wiring line be undercompressive stress.

According to a second aspect of the invention, there is provided asemiconductor structure including a semiconductor base including aplurality of semiconductor devices and a back end of the line wiringlayer. The back end of the line wiring layer includes a wiring line; aninterlayer dielectric (ILD) layer on the wiring line; a via extendingthrough the ILD to communicate with the wiring line, wherein the via hasa via wall; a barrier layer on the via wall; a metal filling the via incontact with the barrier layer and in contact with the wiring line; anda compressive reliability enhancement material surrounding at least partof the metal-filled via to make a bottom of the metal-filled via thatcontacts the wiring line be under compressive stress.

According to a third aspect of the exemplary embodiments, there isprovided a process of making a semiconductor structure which includes:forming a wiring line; forming a recess in the wiring line; filling therecess with a reliability enhancement material; forming a cap layer overthe wiring line and the recess; forming an interlayer dielectric (ILD)layer on the cap layer; forming a via opening through the ILD layer, caplayer and reliability enhancement material to expose a surface of thewiring line; and filling the via opening with a metal to form ametal-filled via in contact with the wiring line; wherein thereliability enhancement material causes a compressive stress on themetal-filled via where it contacts the wiring line.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The features of the exemplary embodiments believed to be novel and theelements characteristic of the exemplary embodiments are set forth withparticularity in the appended claims. The Figures are for illustrationpurposes only and are not drawn to scale. The exemplary embodiments,both as to organization and method of operation, may best be understoodby reference to the detailed description which follows taken inconjunction with the accompanying drawings in which:

FIGS. 1A to 1C illustrate void formation under a via.

FIG. 2 is a cross sectional view of a first embodiment for providingreliability enhancement material around a via.

FIG. 3 is a cross sectional view of a second embodiment for providingreliability enhancement material around a via.

FIG. 4 is a cross sectional view of a third embodiment for providingreliability enhancement material around a via.

FIG. 5 is a cross sectional view of a fourth embodiment for providingreliability enhancement material around a via.

FIG. 6 is a cross sectional view of a fifth embodiment for providingreliability enhancement material around a via.

FIG. 7 is a cross sectional view of a sixth embodiment for providingreliability enhancement material around a via.

FIGS. 8A to 8D illustrate a method for making the fifth embodiment ofFIG. 6.

FIGS. 9A to 9E illustrate a method for making the sixth embodiment ofFIG. 7.

FIGS. 10A to 10E illustrate a first method for making the fourthembodiment of FIG. 5.

FIGS. 11A and 11B illustrate a second method for making the fourthembodiment of FIG. 5.

FIG. 12 illustrate a design process for enhancement of iso-vias in asemiconductor chip design.

FIG. 13 is a block diagram that illustrates an exemplary hardwareenvironment of the computing devices for implementing the design processin FIG. 12.

DETAILED DESCRIPTION

Referring to the Figures in more detail, and particularly referring toFIGS. 1A to 1C, there is shown an example of void formation under a via.FIG. 1A shows a wiring line 10 having a cap layer 12 and interlayerdielectric (ILD) layer 14. A bottom portion, as indicated by arrow 20,of a via 16 makes contact with the wiring line 10. The wiring line 10may have vacancies 18. The bottom portion 20 of the via 16 may be undertensile stress.

Referring now to FIG. 1B, a void 22 has nucleated under the via bottomportion 20 due to the highest tensile stress there. Once the void 22nucleates, a high stress gradient forms around the void 22.

Referring now to FIG. 1C, the vacancies 18 diffuse toward the nucleatedvoid 22, driven by the stress gradient to make the void 22 grow largerunderneath the via 16. Eventually, the void 22 can grow to become anopen or at the very least reduce the contact between the bottom portion20 of via 16 and wiring line 10. If via 16 is an iso-via, then all ofthe stress is concentrated at the one via instead of being spread amongredundant vias. Moreover, if via 16 is an iso-via, failure of via 16means that the circuit including wiring line 10 would also fail.

The present inventors have proposed through post design service andintegration steps to strengthen the vias, to make them less susceptibleto stress migration (SM) or stress voiding (SV) and electromigration(EM). More specifically, the present inventors have proposed changingthe surroundings of the vias to make the metal at the via bottom portionand under the via bottom portion be under compressive stress, ratherthan under tensile stress. By making the via bottom portion and underthe via bottom be under compressive stress:

-   -   a longer time is needed to reach the critical tensile stress for        void formation under and at the via bottom portion;    -   it is also harder for metal void nucleation at the via bottom        portion and/or under the via bottom portion, thereby mitigating        the SM concerns; and    -   the time for void formation incubation time for EM is extended,        needing more metal atoms to migrate away from the via bottom        portion or under the via bottom portion to cause the stress        becoming sufficiently tensile for void nucleation.

In the following description, the “vias” referred to may be redundantvias (two or more vias per wiring line) or iso-vias (only one via perwiring line) but the teachings of the present exemplary embodiments areparticularly relevant to semiconductor structures having iso-vias.

Referring now to FIG. 2, there is illustrated a first exemplaryembodiment of a semiconductor structure 100 which includes a wiring line30, cap layer 32, ILD layer 34 and via 36. The semiconductor structure100 is a portion of the back end of the line wiring structure typicallyfound on a semiconductor chip. In a back end of the line wiringstructure, there will typically be a plurality of semiconductorstructures similar to that shown in FIG. 2 that are stacked to form amultilayer back end of the fine wiring structure. Not shown are thesemiconductor base and front end of the line portion which includes thevarious semiconductor devices such as transistors, capacitors and thelike.

The wiring line 30 may comprise, for example, copper, the cap layer 32may comprise, for example, silicon nitride or silicon carbide plusnitrogen (i.e., less nitrogen than silicon carbide nitride) and the ILDlayer 34 may comprise, for example, an oxide or a low K dielectricconstant material such as SiCOH. The cap layer 32 may be optional but itis usually present in semiconductor structure 100. The semiconductorstructure 100 further includes a via 36 which may include copper. Thewalls of the via 36 may have a barrier layer (not shown) such astantalum/tantalum nitride. In the prior art, the area 38 where the via36 makes contact with the wiring line 30 may be under tensile stresswhich may lead to the SM and EM problems noted above.

Accordingly, the present inventors have proposed a “reliabilityenhancement” material 40 to be placed around the via 36 for at leastpart of the height of via 36. As shown in FIG. 2, the reliabilityenhancement (hereafter “RE”) material surrounds the entire via 36 alongits entire height through the cap layer 32 and ILD layer 34 and exerts acompressive stress on the via 36 at area 38 so as to ameliorate the SM,SV and EM problems of the prior art.

The RE material 40 may be, for example, a silicon nitride (Si_(x)N_(y)),silicon carbide (SiC) or a silicon carbide nitride (Si_(x)C_(y)N_(z))and it may be deposited to be compressive or may be made compressiveafter deposition. If the via 36 has a barrier layer, the barrier layeris between the RE material 40 and the metal (usually copper) filling thevia 36.

Deposition process and treatment conditions may be tailored to deposit acompressive stressed material on the substrate or to treat a materialduring or after deposition to increase its compressive stress value. Forexample, a silicon nitride stressed material having higher compressivestress values may be obtained by increasing the RF bombardment toachieve higher film density by having more Si—N bonds in the depositedmaterial and reducing the density of Si—H and N—H bonds. Higherdeposition temperatures and RF power may also improve the compressivestress levels of the deposited film.

It should be understood that while the cap layer 32 and RE material 40may comprise the same material, RE material 40 is deposited to becompressive or is made compressive after deposition. In addition, REmaterial 40 may be a material that is separate from cap layer 32.

The opening 42 through the cap layer 32 and the ILD layer 34 may beenlarged to accommodate the RE material 40. The RE material 40 is sizedto exert a sufficient force on the via 36 to render the area 38compressive. For example, for a via having a dimension D_(via) where thevia 36 contacts the wiring line 30, the opening 42 should have adimension of D_(RE) where D_(RE) should be at least 2 nanometers greaterthan D_(VIA) so that the wall thickness of the RE material 40 is greaterthan 1 nanometer thick.

It is noted that the outer wall 44 of the RE material 40 is vertical inFIG. 2. Referring now to FIG. 3, the embodiment 120 in FIG. 3 isidentical to the embodiment in FIG. 2 except that the wall 44 of the REmaterial 40 is not vertical and may be inclined at any angle to matchthe inclined angle of the walls of the via 36. In all other respects,the embodiment 120 is similar to embodiment 100 in FIG. 2.

A further embodiment 130 of the invention is illustrated in FIG. 4.Whereas in FIGS. 2 and 3 the RE material 40 surrounded the via 36 andextended the full height of the cap layer 32 and the ILD layer 34, inFIG. 4 the RE material 40 surrounds the via 36 and extends the fullheight of the cap layer 32 and only part way up the height of the ILDlayer 32. In all other respects, the embodiment 130 is similar toembodiment 100 in FIG. 2.

Another embodiment 140 is illustrated in FIG. 5 where the RE material 40surrounds the via 36 and extends only the full height of the cap layer32. It is to be understood that the RE material 40, even though only inthe cap layer 32, is distinguishable from the cap layer 32 becauseeither the RE material 40 may be different from the material of the caplayer 32 or the RE material 40 may be compressive whereas the materialof the cap layer 32 may not be compressive. In all other respects, theembodiment 140 is similar to embodiment 100 in FIG. 2.

Yet another embodiment 150 is illustrated in FIG. 6 in which the REmaterial 40 is only in a portion of the ILD layer 34. In all otherrespects, the embodiment 150 is similar to embodiment 100 in FIG. 2.

A next embodiment 160 is illustrated in FIG. 7 in which the RE material40 is in neither the cap layer 32 nor the ILD layer 34. Rather, the REmaterial 40 is in the wiring line 30 and surrounds the via 36 where thevia 36 makes direct contact with the wiring line 30. In all otherrespects, the embodiment 160 is similar to embodiment 100 in FIG. 2.

Referring now to FIGS. 8A to 8D, there is disclosed a process formanufacturing the embodiment 150 disclosed in FIG. 6. In a first processillustrated in FIG. 8A, wiring line 30 and cap layer 32 are patterned.Then, a layer of RE material is deposited and patterned to result in REmaterial 40 on cap layer 32. In a next process as illustrated in FIG.8B, an ILD layer 34 is deposited on the cap layer 32 and RE material 40.Next, as illustrated in FIG. 8C, a via opening 46 is formed through ILDlayer 34, RE material 40 and cap layer 32 by a process such as reactiveion etching. The wiring line 30 is exposed through the via opening 46.In subsequent process steps illustrated in FIG. 8D, a barrier layer 48may be deposited in the via opening 46 followed by deposition of a metal50, typically copper, to form via 36.

According to this aspect of the exemplary embodiments disclosed in FIGS.8A to 8D, there is provided a process of making a semiconductorstructure which includes: forming a wiring line; forming a cap layer onthe wiring line; forming a reliability enhancement material on the caplayer; forming an interlayer dielectric (ILD) layer on the cap layer andon the reliability enhancement material; forming a via opening throughthe ILD layer, reliability enhancement material and cap layer to exposea surface of the wiring line; and filling the via opening with a metalto form a metal-filled via in contact with the wiring line; wherein thereliability enhancement material causes a compressive stress on themetal-filled via where it contacts the wiring line.

Referring now to FIGS. 9A to 9E, there is disclosed a process formanufacturing the embodiment 160 in FIG. 7. In a first processillustrated in FIG. 9A, the wiring line 30 may be recessed to form arecess 52 such as by wet etching of wiring line 30. Thereafter, in anext process as illustrated in FIG. 9B, RE material 40 may be depositedto fill the recess 52. Any overburden may be removed by a process suchas chemical-mechanical polishing. Thereafter, cap layer 32 and ILD layer34 may be deposited and patterned as illustrated in FIG. 9C. In FIG. 9D,a via opening 54 is formed through ILD layer 34, cap layer 32 and REmaterial 40 by a process such as reactive ion etching. The wiring line30 is exposed through the via opening 54. In subsequent process stepsillustrated in FIG. 9E, a barrier layer 48 may be deposited in the viaopening 54 followed by deposition of a metal 50, typically copper, toform via 36.

According to this aspect of the exemplary embodiments disclosed in FIGS.9A to 9E, there is provided a process of making a semiconductorstructure which includes: forming a wiring line; forming a recess in thewiring line; filling the recess with a reliability enhancement material;forming a cap layer over the wiring line and the recess; forming aninterlayer dielectric (ILD) layer on the cap layer; forming a viaopening through the ILD layer, cap layer and reliability enhancementmaterial to expose a surface of the wiring line; and filling the viaopening with a metal to form a metal-filled via in contact with thewiring line; wherein the reliability enhancement material causes acompressive stress on the metal-filled via where it contacts the wiringline.

Referring now to FIGS. 10A to 10E, there is disclosed a first processfor manufacturing the embodiment 140 in FIG. 5. In a first processillustrated in FIG. 10A, wiring line 30, cap layer 32 and ILD layer 34are deposited and patterned. Thereafter, a via opening 56 is formedthrough ILD layer 34 and cap layer 32 by a process such as reactive ionetching. The wiring line 30 is exposed through the via opening 56. In anext process illustrated in FIG. 10B, portions of the cap layer 32 areremoved by a lateral etch such as an isotropic RIE etch to form recesses58. Thereafter, via opening 56 and recesses 58 are filled with REmaterial 40 as shown in FIG. 100. By an anisotropic RIE etch, the REmaterial 40 is removed except in recesses 58 as shown in FIG. 10D. Insubsequent process steps illustrated in FIG. 10E, a barrier layer 48 maybe deposited in the via opening 54 followed by deposition of a metal 50,typically copper, to form via 36.

According to this aspect of the exemplary embodiments disclosed in FIGS.10A to 10E, there is provided a process of making a semiconductorstructure which includes: forming a wiring line; forming a cap layer onthe wiring line; forming an interlayer dielectric (ILD) layer on the caplayer; forming a via opening through the ILD layer and cap layer toexpose a surface of the wiring line; etching a portion of the cap layerthrough the via opening to form a recess in the cap layer; filling thevia opening and the recess with a reliability enhancement material;etching the reliability enhancement material from the via opening whilemaintaining the reliability enhancement material in the recess; andfilling the via opening with a metal to form a metal-filled via incontact the wiring line; wherein the reliability enhancement materialcauses a compressive stress on the metal-filled via where it contactsthe wiring line.

Referring now to FIGS. 11A and 11B, there is disclosed a second processfor manufacturing the embodiment 140 in FIG. 5. In a first processillustrated in FIG. 11A, wiring line 30, cap layer 32 and ILD layer 34are deposited and patterned. In this case, cap layer 32 is a multiplelayered film comprising a first layer 80 of Si_(x)C_(y)N_(z), asilicon-rich Si_(x)C_(y)N_(z) layer 82 and a third layer 84 ofSi_(x)C_(y)N_(z). The silicon-rich Si_(x)C_(y)N_(z) layer 82 may bedeposited so as to be higher in silicon content than the first and thirdlayers of Si_(x)C_(y)N_(z). The silicon-rich Si_(x)C_(y)N_(z) should beat least 5 atomic percent richer in silicon than the first and thirdlayers of Si_(x)C_(y)N_(z).

Thereafter a via opening 56 is formed through ILD layer 34 and partiallythrough cap layer 32 by a process such as reactive ion etching.Regarding the cap layer 32, the via opening 56 only extends through thefirst layer 80 of Si_(x)C_(y)N_(z) and the silicon-rich Si_(x)C_(y)N_(z)layer 82 and stops on the third layer 84 of Si_(x)C_(y)N_(z). That is,the third layer 84 of Si_(x)C_(y)N_(z) remains on the wiring line 30.The wiring line 30 with the third layer 84 of Si_(x)C_(y)N_(z) isexposed through the via opening 56. The structure shown in FIG. 11A isthen exposed to a high pressure oxidation such as by annealing in a highpressure furnace which contains oxygento oxidize a portion of thesilicon-rich Si_(x)C_(y)N_(z) layer 82 to form SiOCN which swells andputs the portion of the silicon-rich Si_(x)C_(y)N_(z) layer 82 incompression to form RE material 40 as illustrated in FIG. 11B. Insubsequent process steps as illustrated in FIG. 10E, a barrier layer 48may be deposited in the via opening 54 followed by deposition of a metal50, typically copper, to form via 36.

According to this aspect of the exemplary embodiments disclosed in FIGS.11A and 11B, there is provided a process of making a semiconductorstructure which includes: forming a wiring line; forming a cap layer onthe wiring line, the cap layer being a multiple layer structure withfirst, second and third layers of the multiple layer structurecomprising silicon, carbon and nitrogen with the second layer having ahigher silicon content than the first and third layers; forming aninterlayer dielectric (ILD) layer on the cap layer; forming a viaopening through the ILD layer and the first and second layers of the caplayer to expose the third layer of the cap layer on a surface of thewiring line; oxidizing the cap layer so that the second layer comprisesSi, oxygen, carbon and nitrogen and expands with respect to the firstand third layers such that the expanded second layer becomes areliability enhancement material; and filling the via opening with ametal to form a metal-filled via in contact with the wiring line;wherein the reliability enhancement material causes a compressive stresson the metal-filled via where it contacts the wiring line.

Referring now to FIG. 12, there is disclosed a design process forenhancement of iso-via reliability in a semiconductor chip design. In afirst process, design data is received as indicated in box 60. From thedesign data, iso-vias are identified, box 62. A determination is thenmade whether or not enhancement of the iso-via is critical forreliability or yield improvement, box 64. The determination may be madebased on previous experience or reliability results on similarconfigurations. If enhancement of the iso-via is not critical, theprocess branches off to “Do Nothing”, box 66, and the process ends, box74. If enhancement of the iso-via is critical, a marker is added to thevia in the semiconductor chip design to indicate that enhancement isrequired, box 68. The presence of the marker is noted and appropriatesemiconductor processing masks (for example, lithography, etching, etc.)are created, box 70, for incorporating RE material into thesemiconductor chip design. The process then proceeds to create theenforcing features around the iso-vias, box 72, by incorporating REmaterial into the semiconductor chip as it is being manufactured. Any ofthe reliability enhancement material embodiments previously discussedmay be used to enforce the iso-vias. Thereafter, the process ends, box74.

The design process may be implemented on one or computing devices.

According to this aspect of the exemplary embodiments disclosed in FIG.12, there is provided a design process for enhancement of iso-viareliability which includes: receiving design data for a semiconductorchip design having a plurality of iso-vias; identifying the iso-vias inthe semiconductor chip design; determining whether enhancement of theiso-via by incorporating reliability enhancement material around theiso-via in the semiconductor chip design is critical for reliability oryield improvement; responsive to determining that enhancement of theiso-via is critical, adding a marker to the iso-via in the semiconductorchip design to indicate that enhancement of the iso-via is required; andcreating appropriate semiconductor processing masks to provide for theenhancement of the iso-via by incorporating reliability enhancementmaterial around the iso-via in the semiconductor chip design; whereinthe process is performed on one or more computing devices.

The computing devices implementing the design process may be ageneral-purpose computer or a special purpose computing device such as ahand-held computer. FIG. 13 is a block diagram that illustrates oneexemplary hardware environment of the computing devices. The exemplaryembodiments may be implemented using a computer 210 comprised ofmicroprocessor means, random access memory (RAM), read-only memory (ROM)and other components. The computer 210 may be a personal computer,server, mainframe computer, hand-held device or other computing device.Resident in the computer 210, or peripheral to it, may be a storagedevice 214 of some type such as a hard disk drive, floppy disk drive,CD-ROM drive, tape drive or other storage device.

Generally speaking, the software implementation of the exemplaryembodiments, program 212 in FIG. 13, may be tangibly embodied in acomputer-readable medium such as one of the storage devices 214mentioned above. The program 212 may comprise instructions which, whenread and executed by the microprocessor of the computer 210, may causethe computer 210 to perform the steps necessary to execute the steps orelements of the exemplary embodiments.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

It will be apparent to those skilled in the art having regard to thisdisclosure that other modifications of the exemplary embodiments beyondthose embodiments specifically described here may be made withoutdeparting from the spirit of the invention. Accordingly, suchmodifications are considered within the scope of the invention aslimited solely by the appended claims.

What is claimed is:
 1. A semiconductor structure comprising: asemiconductor base comprising a plurality of semiconductor devices: aback end of the line wiring layer comprising: a wiring line; aninterlayer dielectric (ILD) layer on the wiring line; a via extendingthrough the ILD to communicate with the wiring line; a metal filling thevia and in contact with the wiring line; and a compressive reliabilityenhancement material surrounding at least part of the metal-filled viato make a bottom of the metal-filled via that contacts the wiring linebe under compressive stress.
 2. The semiconductor structure of claim 1wherein the reliability enhancement material surrounds the entiremetal-filled via.
 3. The semiconductor structure of claim 1 wherein thereliability enhancement material surrounds the metal-filled via in thecap and only in a portion of the ILD.
 4. The semiconductor structure ofclaim 1 further comprising a cap layer between the wiring line and theILD layer and wherein the reliability enhancement material surrounds themetal-filled via only in the cap layer.
 5. The semiconductor structureof claim 1 wherein the reliability enhancement material surrounds themetal-filled via only in a portion of the ILD.
 6. The semiconductorstructure of claim 1 wherein the reliability enhancement materialsurrounds the metal-filled via only where the metal-filled via contactsthe wiring line.
 7. The semiconductor structure of claim 1 wherein thevia has a via wall and further comprising a barrier layer on the viawall between the via wall and the metal filling the via.
 8. Thesemiconductor structure of claim 1 wherein the reliability enhancementmaterial is selected from the group of materials consisting of siliconnitride, silicon carbide and silicon carbide nitride.
 9. Thesemiconductor structure of claim 1 further comprising a cap layerbetween the wiring line and the ILD layer and wherein the reliabilityenhancement material is selected from the group of materials consistingof silicon nitride, silicon carbide and silicon carbide nitride.
 10. Thesemiconductor structure of claim 9 wherein the cap layer is selectedfrom the group consisting of silicon nitride and silicon carbide plusnitrogen.
 11. The semiconductor structure of claim 9 wherein thereliability enhancement material is separate from the cap layer.
 12. Asemiconductor structure comprising: a semiconductor base comprising aplurality of semiconductor devices: a back end of the line wiring layercomprising: a wiring line; an interlayer dielectric (ILD) layer on thewiring line; a via extending through the ILD to communicate with thewiring line, wherein the via has a via wall; a barrier layer on the viawall; a metal filling the via in contact with the barrier layer and incontact with the wiring line; and a compressive reliability enhancementmaterial surrounding at least part of the metal-filled via to make abottom of the metal-filled via that contacts the wiring line be undercompressive stress.
 13. The semiconductor structure of claim 12 whereinthe reliability enhancement material surrounds the entire metal-filledvia.
 14. The semiconductor structure of claim 12 wherein the reliabilityenhancement material surrounds the metal-filled via in the cap and onlyin a portion of the ILD.
 15. The semiconductor structure of claim 12further comprising a cap layer between the wiring line and the ILD layerand wherein the reliability enhancement material surrounds themetal-filled via only in the cap layer.
 16. The semiconductor structureof claim 12 wherein the reliability enhancement material surrounds themetal-filled via only in a portion of the ILD.
 17. The semiconductorstructure of claim 12 wherein the reliability enhancement materialsurrounds the metal-filled via only where the metal-filled via contactsthe wiring line.
 18. A process of making a semiconductor structurecomprising: forming a wiring line; forming a recess in the wiring line;filling the recess with a reliability enhancement material; forming acap layer over the wiring line and the recess; forming an interlayerdielectric (ILD) layer on the cap layer; forming a via opening throughthe ILD layer, cap layer and reliability enhancement material to exposea surface of the wiring line; and filling the via opening with a metalto form a metal-filled via in contact with the wiring line; wherein thereliability enhancement material causes a compressive stress on themetal-filled via where it contacts the wiring line.
 19. The process ofclaim 18 wherein the reliability enhancement material is deposited so asto be compressive.
 20. The process of claim 18 further comprising afterforming a reliability enhancement material, treating the reliabilityenhancement material so as to be compressive.